Full Adder using component

entity full_adder is
    Port (a : in std_logic;
             b : in std_logic;
             c : in std_logic;
             sum : out std_logic;
             carry : out std_logic);
end full_adder;
architecture Behavioral of full_adder is
component half_adder is
    Port (x : in std_logic;
             y : in std_logic;
             z : out std_logic;
             k : out std_logic);


end component half_adder;
component or is
    Port (m : in std_logic;
             n : in std_logic;
             p : out std_logic);
end component or;
signal s1,c1,c2:std_logic
begin
FA1 : half_adder Port map (a,b,s1,c1);
FA2 : half_adder Port map (s1,c,sum,c2);
FA3 : or Port map (c1,c2,carry);
end Behavioral;